Regviz

Allwinner /D1H /UART[4] /RXDMA_BL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RXDMA_BL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Allwinner/D1H/UART[3]/RXDMA_BL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0buffer_length

Description

UART RXDMA Buffer Length Register

Fields

buffer_length

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data